Rosewill HEARTH NAS PRO | Server Chassis | Supports up to 12 x 3.5" Hot Swap HDD and 6 x 2.5" SSD | E-ATX Compatible

Great review of the Jonsbo N6 NAS Enclosure/Case.

N6 is the latest member of the Jonsbo NAS case series, designed for NAS but not limited to NAS.

The case features a structure that separates the motherboard into upper and lower compartments, offering versatile configuration compatibility, and has a clear and concise internal layout.

Motherboard：ITX / M-ATX

The Baochip-1x is an SoC with enhanced open source and security features. Fabricated in TSMC22ULL, it has a 350MHz Vexriscv RV32-IMAC CPU with Sv39 (virtual memory) support, along with 2MiB of integrated SRAM and 4MiB of integrated RRAM. RRAM is non-volatile memory analogous to FLASH.

The full part number is BAO1X2S4F-WA, but the part is referred to as the “Baochip-1x” or the “bao1x” interchangeably.

Automated provisioning of secure boot and encryption for Raspberry Pi devices

What Problem Does This Solve?

Imagine you need to prepare 100 Raspberry Pi devices for your business.

Each device needs:

• A secure boot system (so only your software can run on it)

• Encrypted storage (so your data is protected)

• Your custom operating system installed

• Security keys programmed correctly

Without this tool, preparing each device manually is time-consuming and error-prone. Each command must be executed precisely. A single mistake requires restarting the entire process.

This tool automates the entire provisioning workflow. Connect a device, and the tool handles all configuration steps automatically. Typical provisioning time is approximately 3 minutes per device (for a 2.6GB OS image).

This X1200-c1 case is designed for the raspberry pi 5 X1201 ups shield only, it can fully accommodate the X1201 and the Raspberry Pi 5, with space reserved on the top for mounting the Raspberry Pi 5 Pip boards, such as the X1001, X1000, X1004, X1003 and M901 etc.

Note: Due to the height limitations of the housing, although the X1201 also supports external switch, but no holes of 12 mm in diameter have been provided for the mounting of an external momentary switch.

For Raspberry Pi 5 + PiSugar 3 Plus + Whisplay Hat + RPi Camera Module 3 (Optional)

Docs for the OAK-D Lite.

Luxonis OAK-D Lite datasheet.

The complete kits include a carbon-fibre QAV250 racing frame, flight controller and almost all other components needed (except battery and receiver).

This topic provides full instructions for building the kit and configuring PX4 using QGroundControl.

Collection of 3D printable components for DEXI drone builds and AVR competition kits.

With a payload capacity of up to 0.5 lbs DEXI offers a range of benefits and opens up various possibilities for both recreational and professional applications.

Mission-Critical Drone Electronics.

The net result is a chip with a lot of compute and a lot of SRAM that is blisteringly fast to access. To put it in numbers, the WSE-3 (Cerebras’ latest chip) has 44GB of on-chip SRAM at 21 PB/s of bandwidth; an H100 has 80GB of HBM at 3.35 TB/s. In other words, the WSE-3 has just over half the memory of an H100, but 6,000 times the memory bandwidth.

The reason to compare the WSE-3 to an H100 is that the H100 is the chip most used for inference — and inference is clearly what Cerebras is most well-suited for. You can use Cerebras chips for training, but the chip-to-chip networking story isn’t very compelling, which is to say that all of that compute and on-chip memory is mostly just sitting around; what is much more interesting is the idea of getting a stream of tokens at dramatically faster speed than you can from a GPU.

Note, however, that the limitation in terms of training also potentially applies in terms of inference: as long as everything fits in on-chip memory Cerebras’ speed is an incredible experience; the moment you need more memory, whether that be for a larger model or, more likely, a larger KV cache, then Cerebras doesn’t make much sense, particularly given the price.

At the same time, I do think there will be a market for Cerebras-style chips: right now the company is highlighting the usefulness of speed for coding — reasoning means a lot of tokens, which means that dramatically scaling up tokens-per-second equals faster thinking — but I think this is a temporary use case, for reasons I’ll explain in a bit. What does matter is how long humans are waiting for an answer, and as products like AI wearables become more of a thing, the speed of interaction, particularly for voice — which will be a function of token generation speed — will have a tangible effect on the user experience.

All of this falls under the banner of “inference”, but I think it will be increasingly clear that there is a difference between providing an answer — what I will call “answer inference” — and doing a task — what I will call “agentic inference.” Cerebras’ target market is “answer inference”; in the long run, I think the architecture for “agentic inference” will look a lot different, not just from Cerebras’ approach, but from the GPU approach as well.

I mentioned above that fast inference for coding is a temporary use case. Specifically, coding with LLMs requires a human in the loop. It’s the human that defines what is to be coded, checks the work, commits the pull request, etc.; it’s not hard to envision a future, however, where all of this is completely handled by machines. This will apply to agentic work broadly: the true power of agents will not be that they do work for humans, but rather that they do work without human involvement at all.

This, by extension, will mean that the likely best approach to solving agentic inference will look a lot different than answer inference. The most important aspect for answer inference is token speed; the most important aspect for agentic inference, however, is memory. Agents need context, state, and history. Some of that will live as active KV cache; some will live in host memory or SSDs; much of it will live in databases, logs, embeddings, and object stores. The important point is that agentic inference will be less about GPUs answering a question and more about the memory hierarchy wrapped around a model.

Critically, this articulation of an agentic-specific memory hierarchy implies a necessary trade-off of speed for capacity. Here’s the thing, though: lower speed isn’t nearly as important a consideration if there isn’t a human in the loop. If an agent is waiting around for a job that is being run overnight, the agent doesn’t know or care about the user experience impact; what is most important is being able to accomplish a task, and if entirely new approaches to memory make that possible, then delays are fine.

Meanwhile, if delays are fine, then all of the focus on pure compute power and high-bandwidth memory seems out of place: if latency isn’t the top priority, then slower and cheaper memory — like traditional DRAM, for example — makes a lot more sense. And if the entire system is mostly waiting on memory, then chips don’t need to be as fast as the cutting edge either. This represents a profound shift in future architectures, but it also doesn’t mean that current architectures are going away:

Cool laptops and desktops for Linux.